Packaging substrate and fabrication method thereof

ABSTRACT

A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to packaging substrates, and moreparticularly, to a packaging substrate and a fabrication method thereoffor improving the product reliability.

2. Description of Related Art

Along with the rapid development of electronic industries, electronicproducts are developed toward the trend of multi-function and highperformance. To improve the wiring precision of multi-layer circuitboards, redistribution layer (RDL) technologies have been developed toalternately stack a plurality of dielectric layers and circuit layers onone another and form a plurality of conductive vias in the dielectriclayers to electrically connect upper and lower circuit layers. Further,coreless packaging technologies have been developed to meet theminiaturization requirement.

FIGS. 1A to 1F are schematic cross-sectional views showing a method forfabricating a packaging substrate 1 according to the prior art.

Referring to FIG. 1A, a carrier 10 is provided and a conductive layer100 is formed on upper and lower sides of the carrier 10.

Referring to FIG. 1B, a first circuit layer 11 is formed on theconductive layer 100 by electroplating. The first circuit layer 11 has aplurality of first conductive pads 110.

Referring to FIG. 1C, a dielectric layer 12 is formed on the carrier 10and the first circuit layer 11.

Referring to FIG. 1D, a second circuit layer 13 is formed on thedielectric layer 12. The second circuit layer 13 has a plurality ofsecond conductive pads 130. Further, a plurality of conductive vias 14are formed in the dielectric layer 12 for electrically connecting thefirst circuit layer 11 and the second circuit layer 13.

Referring to FIG. 1E, the carrier 10 is removed to expose the conductivelayer 100.

Referring to FIG. 1F, the conductive layer 100 is removed to expose thefirst circuit layer 11. Then, a first solder mask layer 15 is formed onan upper side of the dielectric layer 12 and the first circuit layer 11and a plurality of first openings 150 are formed in the first soldermask layer 15 so as to expose the first conductive pads 110 and portionsof the dielectric layer 12 around peripheries of the first conductivepads 110, and a second solder mask layer 16 is formed on a lower side ofthe dielectric layer 12 and the second circuit layer 13 and a pluralityof second openings 160 are formed in the second solder mask layer 16 toexpose the second conductive pads 130.

Subsequently, referring to FIG. 1G an electronic element 9 is disposedon the first conductive pads 110 through a plurality of conductiveelements 18 made of such as a solder material. That is, the conductiveelements 18 come into contact with surfaces 110 a of the firstconductive pads 110. However, such planar contact surfaces lead to smallcontact area between the conductive elements 18 and the first conductivepads 110, thus adversely affecting the bonding strength between theconductive elements 18 and the first conductive pads 110 and easilycausing delamination of the conductive elements 18 from the firstconductive pads 110. Therefore, the product reliability is reduced.

In an embodiment, after the carrier 10 is removed, the first circuitlayer 11 is etched to have a surface lower than that of the dielectriclayer 12. That is, the first circuit layer 11 is recessed into thedielectric layer 12 about 5 um, which however easily causes non-wettingof the conductive elements 18 and consequently causes the conductiveelements 18 to be stuck on the surface of the dielectric layer 12without electrically connecting to the first conductive pads 110.

Therefore, there is a need to provide a packaging substrate and afabrication method thereof so as to overcome the above-describeddrawbacks.

SUMMARY OF THE INVENTION

In view of the above-described drawbacks, the present invention providesa packaging substrate, which comprises: a dielectric layer havingopposite first and second surfaces; a first circuit layer embedded inthe first surface of the dielectric layer and having a surface exposedfrom the first surface of the dielectric layer, wherein the firstcircuit layer has a plurality of first conductive pads; and a pluralityof conductive bumps formed on the first conductive pads and protrudingabove the first surface of the dielectric layer.

In the above-described substrate, the conductive bumps can be made ofcopper.

The present invention further provides a method for fabricating apackaging substrate, which comprises the steps of: providing a carrierhaving a first circuit layer formed thereon, wherein the first circuitlayer has a plurality of first conductive pads; forming a dielectriclayer on the carrier and the first circuit layer, wherein the dielectriclayer has a first surface in contact with and attached to the carrierand a second surface opposite to the first surface; removing the carrierso as to expose a surface of the first circuit layer from the firstsurface of the dielectric layer; and forming on the first conductivepads a plurality of conductive bumps protruding above the first surfaceof the dielectric layer.

In an embodiment, the carrier has a conductive layer that allows thefirst circuit layer to be formed thereon, and the conductive layer isexposed after removing the carrier such that the step of forming theconductive bumps further comprises: forming a metal layer on theconductive layer; and removing portions of the metal layer and theconductive layer under the metal layer so as for the remaining portionsof the metal layer and the conductive layer to form the conductivebumps.

In another embodiment, the carrier has a conductive layer that allowsthe first circuit layer to be formed thereon, and the conductive layeris exposed after removing the carrier such that the step of forming theconductive bumps further comprises: forming a resist layer on theconductive layer and forming a plurality of openings in the resist layercorresponding in position to the first conductive pads; forming a metallayer in the openings of the resist layer; and removing the resist layerso as for the metal layer to form the conductive bumps.

In a further embodiment, the step of forming the conductive bumpsfurther comprises: forming a metal layer on the first surface of thedielectric layer and the surface of the first circuit layer; andremoving portions of the metal layer so as for the remaining portions ofthe metal layer to form the conductive bumps.

In still another embodiment, the surface of the carrier has a metallayer, and after the carrier is removed, portions of the metal layer areremoved so as for the remaining portions of the metal layer to form theconductive bumps.

In the above-described substrate and method, the conductive bumps can beless, equal to or greater in width than the first conductive pads.

In the above-described substrate and method, the surface of the firstcircuit layer can be flush with or lower than the first surface of thedielectric layer.

In the above-described substrate and method, an insulating layer can beformed on the first surface of the dielectric layer and the surface ofthe first circuit layer and have a plurality of openings for exposingthe conductive bumps.

In the above-described substrate and method, a second circuit layer canbe formed on the second surface of the dielectric layer. Further, aplurality of conductive vias can be formed in the dielectric layer forelectrically connecting the first circuit layer and the second circuitlayer. Furthermore, an insulating layer can be formed on the secondsurface of the dielectric layer and the second circuit layer and have aplurality of openings for exposing portions of the second circuit layer.

According to the present invention, when an electronic element isdisposed on the first conductive pads through a plurality of conductiveelements, the conductive elements can come into contact with both topand side surfaces of the conductive bumps so as to increase the contactarea between the conductive elements and the first conductive pads,thereby strengthening the bonding between the conductive elements andthe first conductive pads and preventing delamination of the conductiveelements from the first conductive pads.

Further, even if the surface of the first circuit layer is lower thanthe first surface of the dielectric layer, the conductive bumpsprotruding above the first surface of the dielectric layer ensuresufficient wetting of the conductive elements so as to prevent theconductive elements from being stuck on the first surface of thedielectric layer as in the prior art. Therefore, the conductive elementscan be in effective contact with the conductive bumps so as to beelectrically connected to the first conductive pads.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1F are schematic cross-sectional views showing a method forfabricating a packaging substrate according to the prior art;

FIG. 1G is a schematic cross-sectional view showing a subsequent processof the conventional packaging substrate;

FIGS. 2A to 2G′ are schematic cross-sectional views showing a method forfabricating a packaging substrate according to the present invention,wherein FIGS. 2F′ and 2F″ show other embodiments of the FIG. 2F, andFIG. 2G′ shows another embodiment of FIG. 2G;

FIG. 2H is a schematic cross-sectional view showing a subsequent processof the packaging substrate of the present invention;

FIGS. 3A and 3B are schematic cross-sectional views showing a method forforming the conductive bumps of FIG. 2F;

FIGS. 4A to 4C are schematic cross-sectional views showing anothermethod for forming the conductive bumps of FIG. 2F; and

FIGS. 5A and 5B are schematic cross-sectional views showing a furthermethod for forming the conductive bumps of FIG. 2E

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following illustrative embodiments are provided to illustrate thedisclosure of the present invention, these and other advantages andeffects can be apparent to those in the art after reading thisspecification.

It should be noted that all the drawings are not intended to limit thepresent invention. Various modifications and variations can be madewithout departing from the spirit of the present invention. Further,terms such as “upper”, “lower”, “first”, “second”, “a” etc. are merelyfor illustrative purposes and should not be construed to limit the scopeof the present invention.

FIGS. 2A to 2G are schematic cross-sectional views showing a method forfabricating a packaging substrate 2 according to the present invention.

Referring to FIGS. 2A and 2B, a carrier 20 is provided and a firstcircuit layer 21 is formed on upper and lower surfaces of the carrier20.

The carrier 20 can be an insulating plate, a ceramic plate, a copperclad laminate or a glass plate. In the present embodiment, a metal layer200 is formed on the upper and lower surfaces of the carrier 20 to serveas a conductive layer, i.e., a seed layer. If the carrier 20 is a copperclad laminate, the copper foil of the copper clad laminate can serve asthe conductive layer.

Referring to FIG. 2B, a first circuit layer 21 is formed on theconductive layer 200 by electroplating. The first circuit layer 21 has aplurality of first conductive pads 210.

Referring to FIG. 2C, a dielectric layer 22 is formed on the carrier 20and the first circuit layer 21. The dielectric layer 22 has a firstsurface 22 a in contact with and attached to the carrier 20 and a secondsurface 22 b opposite to the first surface 22 a.

In the present embodiment, the dielectric layer 22 is made of prepreg.

Referring to FIG. 2D, a second circuit layer 23 is formed on the secondsurface 22 b of the dielectric layer 22. The second circuit layer 23 hasa plurality of second conductive pads 230. Further, a plurality ofconductive vias 24 are formed in the dielectric layer 22 forelectrically connecting the first circuit layer 21 and the secondcircuit layer 23.

Referring to FIG. 2E, the carrier 20 is removed to expose the conductivelayer 200.

Referring to FIG. 2F, a plurality of conductive bumps 27 made of such ascopper are formed on the conductive layer 200 corresponding in positionto the first conductive pads 210. The conductive bumps 27 protrude to aheight h of 5 um above the first surface 22 a of the dielectric layer22. Then, portions of the conductive layer 200 exposed from theconductive bumps 27 are removed while maintaining portions 200′ of theconductive layer 200 under the conductive bumps 27.

In the present embodiment, the width D of the conductive bumps 27 isequal to the width R of the first conductive pads 210.

In another embodiment, referring to FIG. 2F′, the width D′ of theconductive bumps 27′ is greater than the width R of the first conductivepads 210. In a further embodiment, referring to FIG. 2F″, the width D″of the conductive bumps 27′ is less than the width R of the firstconductive pads 210.

Referring to FIG. 2G, a first insulating layer 25 is formed on the firstsurface 22 a of the dielectric layer 22 and the first circuit layer 21and a plurality of first openings 250 are formed in the first insulatinglayer 25 so as to expose the conductive bumps 27 and portions of thefirst surface 22 a of the dielectric layer 22 around peripheries of theconductive bumps 27. Further, a second insulating layer 26 is formed onthe second surface 22 b of the dielectric layer 22 and the secondcircuit layer 23 and a plurality of second openings 260 are formed inthe second insulating layer 26 to expose the second conductive pads 230.

In another embodiment, referring to FIG. 2G′, when the conductive layer200 is removed, the first conductive pads 210 are also partially removedso as to be recessed into the first surface 22 a of the dielectric layer22.

Subsequently, referring to FIG. 2H, an electronic element 9 is disposedon the first conductive pads 210 through a plurality of conductiveelements 28 made of such as a solder material. Since the conductivebumps 27 protrude above the first surface 22 a of the dielectric layer22, the conductive elements 28 can come into contact with both topsurfaces 27 a and side surfaces 27 c of the conductive bumps 27 so as toincrease the contact area between the conductive elements 28 and thefirst conductive pads 210, thereby strengthening the bonding between theconductive elements 28 and the first conductive pads 210 and preventingdelamination of the conductive elements 28 from the first conductivepads 210. Therefore, the product reliability is improved.

Further, even if the surface of the first circuit layer 21 is lower thanthe first surface 22 a of the dielectric layer 22, the conductive bumps27 protruding above the first surface 22 a of the dielectric layer 22ensure sufficient wetting of the conductive elements 28 so as to preventthe conductive elements 28 from being stuck on the first surface 22 a ofthe dielectric layer 22. Therefore, the conductive elements 28 can be ineffective contact with the conductive bumps 27 so as to be electricallyconnected to the first conductive pads 210.

The conductive bumps 27 can be formed through the following methods.

FIGS. 3A and 3B are schematic cross-sectional views showing a method forforming the conductive bumps 27 according to a first embodiment.

Referring to FIG. 3A, a metal layer 40 is formed on the conductive layer200 by attaching or electroplating.

In the present embodiment, the conductive layer 200 is a copper foil.

Referring to FIG. 3B, a patterning process is performed to removeportions of the metal layer 40 and the conductive layer 200 under themetal layer 40. As such, the remaining portions 40′ of the metal layer40 and the remaining portions 200′ of the conductive layer 200 form theconductive bumps 27.

FIGS. 4A to 4C are schematic cross-sectional views showing a method forforming the conductive bumps 27 according to a second embodiment.

Referring to FIG. 4A, a resist layer 52 is formed on the conductivelayer 200 and a plurality of third openings 520 are formed in the resistlayer 52 to expose portions of the conductive layer 200 corresponding inposition to the first conductive pads 210.

In the present embodiment, the conductive layer 200 is a copper foil.

Referring to FIG. 4B, a metal layer 50 is formed on the exposed portionsof the conductive layer 200 in the third openings 520 of the resistlayer 52 by electroplating.

Referring to FIG. 4C, the resist layer 52 and the portions of theconductive layer 200 under the resist layer 52 are removed. As such, themetal layer 50 and the portions 200′ of the conductive layer 200 underthe metal layer 50 form the conductive bumps 27.

FIGS. 5A and 5B are schematic cross-sectional views showing a method forforming the conductive bumps 27 according to a third embodiment.

Referring to FIG. 5A, the conductive layer 200 is removed and a metallayer 30 is formed on the first surface 22 a of the dielectric layer 22and the first circuit layer 21.

In the present embodiment, a copper foil can be laminated on the firstsurface 22 a of the dielectric layer 22 and the first circuit layer 21to serve as the metal layer 30. Alternatively, the metal layer 30 can beformed by electroplating.

In other embodiments, after the conductive layer 200 is removed, thefirst circuit layer 21 has a surface slightly lower than the firstsurface 22 a of the dielectric layer 22 so as to be recessed into thefirst surface 22 a of the dielectric layer 22.

In another embodiment, no conductive layer 200 is formed on the upperand lower surfaces of the carrier 20. Instead, referring to FIG. 5A, themetal layer 30 is directly formed on the upper and lower surfaces of thecarrier 20. Therefore, after the carrier 20 is removed, the metal layer30 is exposed.

Referring to FIG. 5B, a patterning process is performed to removeportions of the metal layer 30. As such, the remaining portions 30′ ofthe metal layer 30 form the conductive bumps 27.

The present invention further provides a packaging substrate 2, whichhas: a dielectric layer 22 having opposite first and second surfaces 22a, 22 b; a first circuit layer 21 embedded in the first surface 22 a ofthe dielectric layer 22 and having a surface exposed from the firstsurface 22 a of the dielectric layer 22, wherein the first circuit layer21 has a plurality of first conductive pads 210; and a plurality ofconductive bumps 27, 27′, 27″ formed on the first conductive pads 210and protruding above the first surface 22 a of the dielectric layer 22.

The surface of the first circuit layer 21 can be flush with the firstsurface 22 a of the dielectric layer 22.

The conductive bumps 27, 27′, 27″ can be less, equal to or greater inwidth than the first conductive pads 210. The conductive bumps 27, 27′,27″ can be made of copper.

The packaging substrate 2 can further have a first insulating layer 25formed on the first surface 22 a of the dielectric layer 22 and thesurface of the first circuit layer 21 and having a plurality of openings250 for exposing the conductive bumps 27, 27′, 27″ and portions of thefirst surface 22 a around peripheries of the conductive bumps 27, 27′,27″.

The packaging substrate 2 can further have a second circuit layer 23formed on the second surface 22 b of the dielectric layer 22 and havinga plurality of second conductive pads 230. Further, a plurality ofconductive vias 24 are formed in the dielectric layer 22 forelectrically connecting the first circuit layer 21 and the secondcircuit layer 23. Furthermore, the packaging substrate 2 can have asecond insulating layer 26 formed on the second surface 22 b of thedielectric layer 22 and the second circuit layer 23 and having aplurality of second openings 260 for exposing the second conductive pads230.

According to the present invention, since the first conductive pads havethe conductive bumps formed thereon and protruding above the firstsurface of the dielectric layer, when an electronic element is disposedon the first conductive pads through a plurality of conductive elementsmade of such as a solder material, the conductive elements can come intocontact with a plurality of surfaces of the conductive bumps so as toincrease the contact area between the conductive elements and the firstconductive pads, thereby strengthening the bonding between theconductive elements and the first conductive pads and preventingdelamination of the conductive elements from the first conductive pads.Therefore, the product reliability is improved.

Further, even if the surface of the first circuit layer is lower thanthe first surface of the dielectric layer, the conductive bumpsprotruding above the first surface of the dielectric layer ensuresufficient wetting of the conductive elements so as to cause theconductive elements to be in effective contact with the conductive bumpsso as to be electrically connected to the first conductive pads, therebyimproving the product reliability.

The above-described descriptions of the detailed embodiments are only toillustrate the preferred implementation according to the presentinvention, and it is not to limit the scope of the present invention.Accordingly, all modifications and variations completed by those withordinary skill in the art should fall within the scope of presentinvention defined by the appended claims.

What is claimed is:
 1. A packaging substrate, comprising: a dielectriclayer having opposite first and second surfaces; a first circuit layerembedded in the first surface of the dielectric layer and having asurface exposed from the first surface of the dielectric layer, whereinthe first circuit layer has a plurality of first conductive pads; and aplurality of conductive bumps formed on the first conductive pads andprotruding above the first surface of the dielectric layer.
 2. Thesubstrate of claim 1, wherein the surface of the first circuit layer isflush with or lower than the first surface of the dielectric layer. 3.The substrate of claim 1, further comprising an insulating layer formedon the first surface of the dielectric layer and the surface of thefirst circuit layer and having a plurality of openings for exposing theconductive bumps.
 4. The substrate of claim 1, further comprising asecond circuit layer formed on the second surface of the dielectriclayer.
 5. The substrate of claim 4, further comprising a plurality ofconductive vias formed in the dielectric layer for electricallyconnecting the first circuit layer and the second circuit layer.
 6. Thesubstrate of claim 4, further comprising an insulating layer formed onthe second surface of the dielectric layer and the second circuit layerand having a plurality of openings for exposing portions of the secondcircuit layer.
 7. The substrate of claim 1, wherein the conductive bumpsare less, equal to or greater in width than the first conductive pads.8. The substrate of claim 1, wherein the conductive bumps are made ofcopper.
 9. A method for fabricating a packaging substrate, comprisingthe steps of: providing a carrier having a first circuit layer formedthereon, wherein the first circuit layer has a plurality of firstconductive pads; forming a dielectric layer on the carrier and the firstcircuit layer, wherein the dielectric layer has a first surface incontact with and attached to the carrier and a second surface oppositeto the first surface; removing the carrier so as to expose a surface ofthe first circuit layer from the first surface of the dielectric layer;and forming on the first conductive pads a plurality of conductive bumpsprotruding above the first surface of the dielectric layer.
 10. Themethod of claim 9, wherein the surface of the first circuit layer isflush with or lower than the first surface of the dielectric layer. 11.The method of claim 9, wherein the carrier has a conductive layer thatallows the first circuit layer to be formed thereon, and the conductivelayer is exposed after removing the carrier such that the step offorming the conductive bumps further comprises: forming a metal layer onthe conductive layer; and removing portions of the metal layer and theconductive layer under the metal layer so as for the remaining portionsof the metal layer and the conductive layer to form the conductivebumps.
 12. The method of claim 9, wherein the carrier has a conductivelayer that allows the first circuit layer to be formed thereon, and theconductive layer is exposed after removing the carrier such that thestep of forming the conductive bumps further comprises: forming a resistlayer on the conductive layer and forming a plurality of openings in theresist layer corresponding in position to the first conductive pads;forming a metal layer in the openings of the resist layer; and removingthe resist layer so as for the metal layer to form the conductive bumps.13. The method of claim 9, wherein the step of forming the conductivebumps further comprises: forming a metal layer on the first surface ofthe dielectric layer and the surface of the first circuit layer; andremoving portions of the metal layer so as for the remaining portions ofthe metal layer to form the conductive bumps.
 14. The method of claim 9,wherein the carrier has a metal layer, and after the carrier is removed,portions of the metal layer are removed so as for the remaining portionsof the metal layer to form the conductive bumps.
 15. The method of claim9, further comprising forming an insulating layer on the first surfaceof the dielectric layer and the surface of the first circuit layer andforming a plurality of openings in the insulating layer for exposing theconductive bumps.
 16. The method of claim 9, further comprising forminga second circuit layer on the second surface of the dielectric layer.17. The method of claim 16, further comprising forming a plurality ofconductive vias in the dielectric layer for electrically connecting thefirst circuit layer and the second circuit layer.
 18. The method ofclaim 16, further comprising forming an insulating layer on the secondsurface of the dielectric layer and the second circuit layer and forminga plurality of openings in the insulating layer for exposing portions ofthe second circuit layer.
 19. The method of claim 9, wherein theconductive bumps are less, equal to or greater in width than the firstconductive pads.